Revolutionizing Advanced Packaging: The Ultimate Integrated Design Ecosystem for Chiplets and Heterogeneous Integration

With the growing need for high-performance computing (HPC), chiplets and heterogeneous integration are becoming essential. They offer great benefits like better yields, IP reuse, improved performance, and cost savings. For AI applications, chiplets require many more connections than traditional single-chip designs. These connections need to be dense, efficient for data transfer, and effective in power delivery. This has increased the demand for advanced packaging with more interconnects and larger sizes. In fact, the layout density in these modern packages can be tens or even hundreds of times greater than older FCBGA packages. However, this complexity brings new challenges for packaging design and assembly processes.

Challenges in Package Design for Chiplets

In the past, the design of integrated circuits (ICs) and packages was done separately. But, as we move towards multi-chiplet architectures, connecting chiplets effectively is becoming trickier. This transition makes the design process more complicated. Many chiplet connections are proprietary, which adds further restrictions and slows down the use of advanced packaging techniques.

For example, a typical FCBGA package for a single chip is about 62.5 x 62.5 mm² and has around 30,000 I/O pins. When chiplets are used—like an ASIC chip paired with high-bandwidth memory (HBM)—an interposer is needed. Even if the package size doesn’t change, the number of pins can jump to around 160,000.

Creating high-density routing for the silicon interposer brings up new design rules that traditional tools may not handle well. This can make the design cycle take ten times longer than for standard monolithic packages.

For monolithic designs, the focus has often been on PCB and substrate design, while chip design was left to the foundries. However, chiplet integration requires a more complete view. We need platforms that allow for system-level optimizations in power, performance, and area (PPA), pulling data from different design fields.

Introducing the Integrated Design Ecosystem

To tackle the challenges of chiplet package design, we’ve launched the Integrated Design Ecosystem (IDE). This tool improves design efficiency and quality, speeding up time-to-market for our clients. The IDE features cross-platform interaction for layout and verification, automated routing for interposers, and design rule checks (DRC), along with a Package Design Kit (PDK).

The IDE supports various chiplet connection standards, allowing diverse chiplet designs to work together smoothly. Compared to older platforms, the IDE can boost design efficiency by up to 50% while improving accuracy.

How IDE Fits Into ASE’s Workflow

The IDE is perfect for optimizing chiplet designs using our FOCoS RDL interposer or 2.5D Si interposer. The process starts with substrate design using a classic package design tool, which creates a global file. Next, we use an IC design tool for interposer design and then go back to the package tool for RDL optimization and GDS file creation for validation. Lastly, we employ an automated mask design process for manufacturing.

Using traditional tools, RDL routing of a netlist can take weeks. But with our automated router, we can cut the layout design time by over 50%. Plus, our automated mask generator reduces RDL mask design time from days to under an hour.

Complete Solutions for Chiplets and Heterogeneous Integration

As technology rapidly evolves, chiplets and heterogeneous integration are enhancing system performance and advancing Moore’s law. They also enable AI’s significant role in HPC, AI/ML, cloud computing, automotive tech, and 5G. To facilitate widespread use, chiplets need to be interoperable and easy to connect. The ASE Integrated Design Ecosystem provides a comprehensive solution covering everything from interposer design to manufacturing feasibility, ensuring successful integration of multiple chiplets in a single package while maximizing system performance.